::::::English Description::::::
Timing closure in today抯 advanced designs remains the number one challenge for designers today, especially at 90-nanometers (nm) and below. A trusted timing sign-off solution that accurately models and predicts silicon behavior is required to enable designers to quickly achieve timing closure.
The PrimeTime STA Solution
The Synopsys PrimeTime static timing analysis solution is the most trusted and advanced timing sign-off solution for gate-level designs. It is the industry抯 de-facto gold standard for gate-level static timing analysis and is a key component of the Galaxy?Design Platform.
With a wide breadth of sign-off analysis capabilities, the PrimeTime STA solution provides a comprehensive and unmatched environment for timing sign-off and serves as an industry yardstick for timing analysis and sign-off. It delivers to designers extensive timing analysis checks, advanced analysis techniques, golden delay calculator, advanced modeling, unmatched productivity and ease of use, a graphical user interface, and industry-wide ASIC vendor sign-off and foundry support.
The PrimeTime Suite
The trusted PrimeTime static timing analysis solution provides the foundation and environment for a suite of extensions in sign-off analysis. In addition to timing analysis, the PrimeTime SI, PrimeTime PX, and PrimeTime VX solutions deliver extensions for signal integrity analysis, leakage and dynamic power analysis, and variation-aware analysis.
- Setup/hold/recovery/removal checks
- Data-to-data timing checks
- Clock gating setup and hold checks
- No change checks
- Bus contention and float checks
- Maximum transition checks
- Minimum pulse width checks
- Maximum fanout and capacitance checks
- User-defined maximum and minimum delay checks
- Input/output delay, input transition, port driving cell, output
- load support
- Multi-clock support
- Multi-cycle and false path exception support
- Transparent latch and time borrowing support
- Generated or derived clock support
- Clock latency, clock skew, clock uncertainty support
- Pulse clock support
- Case analysis
- Mode analysis
- Analysis coverage report of timing checks
- Parasitic or SDF delay annotations
- User-defined delay and transition annotations
- Extensive design, constraint, annotation, and delay reporting
- Advanced Analysis Techniques
- On-chip-variation (OCV) analysis
- Clock reconvergence pessimism removal
- Multiple clocks per register
- Automatic false path detection
- Dynamic feedback loop breaking
- Worst arrival slew propagation
- Path-specific recalculation and analysis
- Bottleneck analysis
- What-if ECO analysis
- ECO netlist editing
- Global and instance-specific timing derating
- Global and net-specific timing derating
- Instance location (x,y) coordinates from SPEF
- Exclusive and asynchronous clock groups
- Timing exception optimization
- User-defined operation conditions (PVT)
- PrimeTime SI for signal integrity analysis
- PrimeTime PX for dynamic and leakage power analysis
- PrimeTime VX for variation-aware analysis
- Golden Delay Calculator
- Built-in RC delay calculation uses parasitics information for accurate interconnect analysis
- SPEF, DSPF, and RSPF file format support
- SBPF (Synopsys Binary Parasitic Format) support
- CCS and NLDM Liberty library support
- SDF output and custom SDF mapping
- SPICE deck output
- Worst-arrival slew propagation
- Multi-voltage support
- Instance-specific rail voltages
- Global and net-specific parasitic scaling
- Voltage scaling between libraries
- Temperature scaling between libraries
- Library-specific delay and slew and thresholds
- Pin-specific delay and slew thresholds
- Extensive delay calculation and parasitic annotation reporting
- Advanced Modeling
- Interface Logic Models (ILM) for hierarchical static timing analysis and sign-off
- Extracted Timing Models (ETM) in .lib format for cell-based reusable IP and physical design flows
- Quick Timing Models (QTM) for top-down design
- Automatic model validation
- ETM debugging
- ETM model merging
- Hierarchical block scope analysis
- Productivity and Ease of Use
- 64-bit architecture for full-chip timing analysis of 100-million gates
- Incremental timing engine
- Save and restore
- Distributed multi-scenario analysis with intelligent merged reporting
- What-if ECO analysis
- Exception and constraint analysis for debugging
- Tcl shell with command line editing
- Tcl support (collections, scripting, etc.)
- Direct reading and writing of gzip compressed files
- Extensive reporting options
- Extensive built-in attributes for custom scripting and reporting
- User-defined attributes
- Graphical User Interface
- Timing analysis and design visualization using schematics, histograms, tables, and tree graphs
- Full hierarchical schematic
- Timing path schematic, table, and profiler
- Clock network schematic and table
- Clock domain interaction matrix table
- Timing bottleneck identification and visualization
- Path recalculation table
- Design attribute table
- Slack and design data histograms
- Customizable histograms
- Start-up from Tcl shell
- ASIC vendor sign-off and foundry support
- Agere
- Fujitsu
- LSI Logic
- NEC
- Renesas
- Samsung
- STMicroelectronics
- Texas Instruments
- Toshiba
- TSMC
- UMC
- Chartered Semiconductor Manufacturing
- IBM Foundry
- SMIC
- Input/Output Formats
- Netlists: Verilog, VHDL, Synopsys DDC format
- Constraints: PrimeTime constraints, SDC
- Parasitics and Delay: SPEF, DSPF, RSPF, SBPF, SDF
product:Synopsys PrimeTime 2009.06 Linux
Lanaguage:english
Platform:Winxp/Win7
Size:413MB