Synopsys Formality vO-2018.06 SP1
Formality and Formality Ultra
Verifies the Toughest Designs Synthesized with Design Compiler
Formality® is an equivalence-checking (EC) solution that uses formal, static techniques to determine if two versions of a design are functionally equivalent. The size and complexity of today’s designs, coupled with the challenges of meeting timing, area, power and schedule, requires that the newest, most advanced synthesis optimizations be fully verifiable. Formality supports all DC Ultra and Design Compiler Graphical optimizations and so provides the highest quality of results that are fully verifiable. Formality supports verification of power-up and power-down states, multi-voltage, multi-supply and clock gated designs.
Formality Ultra adds innovative matching and verification technologies to efficiently guide designers through the implementation of functional ECOs with minimal impact to the design and verify the correctness of the ECOs in minutes for multimillion instance designs. These capabilities help designers cut in half the time they spend implementing ECOs late in the design cycle and result in shorter, more predictable schedules.
Formality’s easy-to-use, flow-based graphical user interface and auto-setup mode helps even new users successfully complete verification in the shortest possible time.
Perfect companion to DC Ultra/Design Compiler Graphical — supports all default optimizations
Intuitive flow-based graphical user interface
Verifies low-power designs including power-up and power-down states
Formality Ultra adds ECO implementation assistance, fast verification of the ECO, and advanced debugging to Formality
Auto setup mode reduces “false failures” caused by incorrect or missing setup information
Multicore verification boosts performance
Automated guidance boosts completion with DC Ultra/Design Compiler Graphical
Verifies full-custom and memory designs when including ESP technology
Formality: The Most Comprehensive Equivalence Checking Solution
Formality delivers superior completion on designs compiled with DC Ultra/Design Compiler Graphical, which uses Topographical Technology to achieve accurate correlation with post-layout timing, area and power, and provides advanced optimizations such as retiming, phase inversion and ungrouping. Formality is also fully compatible with Design Compiler Graphical used to predict and alleviate routing congestion. Designers no longer need to disable Design Compiler’s powerful optimizations to get equivalence checking to pass. DC Ultra/Design Compiler Graphical combined with Formality delivers maximum quality of results (QoR) that are fully verifiable.
product:Synopsys Formality vO-2018.06 SP1