Synopsys IC Compiler vO-2018.06 for linux
Place and Route System
The IC Compiler™ place and route system is a single, convergent, chip-level physical implementation tool. It includes flat and hierarchical design planning, placement, clock tree synthesis, routing and optimization, manufacturability, and low-power capabilities that enable on schedule delivery of advanced designs. For Synopsys’ latest place-and-route system refer to IC Compiler II.
IC Compiler is a complete place-and-route system for established and emerging process technology node designs.
IC Compiler hierarchical design technology enables powerful design planning and early chip level exploration/analysis features to handle large, complex designs.
IC Compiler delivers smaller die size with predictable design closure to reduce the cost of design.
IC Compiler with Zroute digital router technology utilizes advanced routing algorithms, concurrent manufacturability optimizations and multi-threading, to improve manufacturability and deliver faster turn-around-time.
IC Compiler In-Design technology seamlessly integrates the IC Validator signoff DRC and metal fill solution allowing designers to mitigate manufacturing compliance challenges in the implementation stage for faster signoff closure.
IC Compiler is part of the Synopsys Design Platform and is tightly correlated to the industry-standard signoff solutions — PrimeTime® SI and StarRCTM with value links to Design Compiler® Graphical.
product:Synopsys IC Compiler vO-2018.06