NanoSim™ is the cornerstone of Synopsys’ comprehensive mixed-signal verification solution, Discovery AMS. NanoSim is an advanced transistor-level circuit simulation and analysis tool for analog, digital and mixed-signal design verification. It is a robust and easy to use solution, with very high simulation throughput and capacity for multi-million transistor SoC’s and accuracy for designs at 90 nanometer and below.
* Provides high accuracy for designs at 90 nanometer and below
* Simulation speeds up to orders of magnitude faster than SPICE
* Capacity to simulate large memory and SoC designs, e.g. 512 Mb DRAM with 1 Billion elements
* Provides flexibility to trade-off accuracy versus performance
* Seamless integration with parasitic extraction tool, Star-RCXT for efficient post-layout simulation
* Fits in any methodology with its support for all major SPICE netlist and model formats
* Ease of adoption using intuitive GUI based setup and simulation environment
* Boosts productivity with comprehensive built-in timing and power diagnostic functions
NanoSim Technology: Accuracy, Performance & Capacity Leader
NanoSim combines best-in-class simulation technologies from TimeMill® and PowerMill® to deliver combined timing and power analysis and diagnostics in a single tool. It is a completely backward compatible solution with TimeMill/PowerMill, accepting the same netlist and setup, with the quality of results guaranteed to be the same.
Some key aspects of NanoSim proprietary technology are:
* Intelligent partitioning and synchronization of design parallelizes computations
* Combination of event- and time- based simulation delivers speed without sacrificing accuracy
* Automatic topology detection and application of optimal simulation mode
* Uses same device models similar as HSPICE assuring high accuracy
* Accurate modeling of DSM effects such voltage dependent Miller terms, crosstalk analysis and ground bounce effects
* Simulation modes ranging from PWL for digital circuits to SPICE like Analytic mode
* Direct read of parasitic data in DSPF or SPEF formats
* Advanced RC compaction algorithm, LNS that maintains network passivity and preserves coupling capacitance providing high performance for post-layout designs
* Netlist Input: SPICE, Verilog, EDIF, LSIM, SPF, SPEF
* Stimulus: .vec, Verilog HDL testbenches (VCS required)
* Models: BJTs, BSIM3.x, BSIM 4.x MM905, JFET, MESFET, HVMOS*, SiGe VBIC, SOI, etc.
* Use of pre-characterized technology files for faster run times
* Output: .out, turboWave .fsdb and API for custom output into other display tools.
product:Synopsys NanoSim 2010