CustomExplorer™ and Custom WaveView™ form a comprehensive transistor-level debugging environment for analog, mixed-signal and SoC designs. CustomExplorer provides a host of tools for navigating transistor-level designs and verifying simulation results.
CustomExplorer is tightly integrated with Custom WaveView, enabling customizable waveform analysis. Custom WaveView provides powerful tools for displaying waveforms, performing calculations and making measurements (see Figure 1). Together, these tools aid designers in rapidly performing customized advanced analyses in a highly-productive design debugging and waveform analysis environment.
CustomExplorer Design Browsers
The Design Browsers allow quick access to the most complex hierarchy design data. After loading a netlist or simulation results, the user can probe the design’s hierarchy by expanding the Lint, File, Deck, Flat or Output View tabs. These views, shown in Figure 2, work in concert and provide rapid access to all of the contents of the design or of a given level of hierarchy whether working with SPICE or DSPF netlists or a mix of both.
SPICE Lint View
CustomExplorer’s SPICE Lint View performs compatibility checks that can be used to verify that the netlists being simulated conform to the proper syntax before wasting time on a long simulation before finding a problem. These checks are performed automatically as the netlist is read in with all errors or warnings being flagged in the SPICE Lint Window.
* Simulator Control Option Checks
Verifies that the proper syntax has been used for all simulator analyses preventing wasted simulation time
* Parameter Passing Rule Checks
Verifies that all parameters are properly defined before use and properly passed through the hierarchy. Parameters that are redefined or recursively defined are also found
* Element Parameter Rule Checks
The element parameter rule checks also finds and flags parameter values that are set above user definable thresholds. This includes looking for element parameter Negative capacitance/resistance, model selector problems, irregular element values and sizes, non–positive subcircuit multiplier and PWL stimuli statements with sharp slews
* Design Connectivity Rule Checks
Finds and flags problems with floating nodes or blocks, global nodes that are not driven by any source, DC-floating MOS gate and nodes, dangling element terminals, and floating transient sources. This helps the designer to deliver a quality netlist to the simulator of choice
Netlists for custom digital and AMS designs can be very large and complex. The File View window shows the collection of files that are referenced in the top-level netlist including complete paths to those files. CustomExplorer follows all .Include and .Lib statements to ensure that all parts of the netlist are checked.
The Deck View tab displays the hierarchical content of the design netlist allowing the designer to query the contents of a design or cell. Selecting a subcircuit in the Deck View displays the contents of that subcircuit as well as displaying the interface pins and netnames, and parameters in the Cell View.
Cell View Window
Selecting a component or subcircuit in the Deck or Flat View tabs presents the user with a picture of that object in the Cell View window. Included in the diagram are the name of the object, its terminal names and the nets that connect to it. In the case of subcircuits, the internal netnames are also displayed making it easy to follow nets up and down the hierarchy through subcircuit boundaries. CustomExplorer’s Net Tracer can also be used to follow changing netnames with ease through the design’s hierarchy.
product:Synopsys CustomExplorer 2010.12