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Synopsys NanoTime 2009.06 Linux

The Challenge
Accurate transistor-level analysis of crosstalk-delay
As designs go down to 90-nm and below, crosstalk-delay becomes more than 25%
of total delay. Prior solutions including traditional static timing analysis with optional
3rd party crosstalk delay analysis do not provide the accuracy and productivity that
is required. Concurrent timing and SI is a must to achieve silicon success.
Full chip timing verification
Transistor- and gate-level static timing analysis need to work together to achieve
full chip timing verification (i.e) a seamless and accurate timing analysis flow
from custom design to gate-level with PrimeTime is required. To achieve higher
productivity, NanoTime has the same commands as PrimeTime whenever they
are applicable.
Concurrent timing and signal-
integrity (SI) analysis provides higher
predictability and better productivity
over existing solutions. NanoTime
offers integrated timing and crosstalk-
delay analysis to achieve higher silicon
With its unmatched ability to recognize
complex custom design structures,
embedded NanoSim technology
for dynamic circuit evaluation and
the state-of-the-art RC reduction
algorithm, NanoTime delivers accuracy
within 5% of HSPICE
Ease of use features improves
productivity. The ease-of-use
features include easy setup with Tcl,
the Synopsys common command
interpreter; interactive timing analysis
that allows multiple analyses in
a single session and a seamless
flow with PrimeTime that supports
Synopsys Design Constraints (SDC).
New algorithms that result in a five-
fold increase in performance over
existing solution without sacrificing
product:Synopsys NanoTime 2009.06 Linux