Synopsys Testchip 2006.12 Linux

::::::English Description::::::

Synopsys?TechXpress™ products enable a revolutionary amount of process insight in a minimum amount of silicon area that is not possible with conventional characterization technologies. A decade of experience in leading-edge technology development and yield optimization has shaped the TechXpress product line to enable the types and volumes of information that are required for successful nanometer-era technology development.

Solutions Span Entire Semiconductor Process Life Cycle

TechXpress solutions span the entire semiconductor process life cycle. Solutions are grouped into four chip sets that are used by process integration and yield engineers to target the specific tasks found at each stage of the process life cycle. The chips sets are classified as, ToolBox (for early materials and litho characterization), RaceTrack (for technology development, process integration and primary parameter characterization), OnRamp (for parametric, systematic and random defectivity based yield ramp) and Expressway (for parametric and systematic yield monitoring). Within each chip set are test vehicles that target all key areas of nanometer-era Front-End-of-Line (FEOL) and Back-End-of-Line (BEOL) process integration and ramp, that have proven to be effective from 180 nm to 45 nm. These vehicles are used in combination with Synopsys?next generation TestChip Advantage™ analysis software to analyze – with ease – complex random, systematic and parametric process interactions.

TestChip Advantage Analysis Software
TestChip Advantage is a sophisticated analysis and data reduction software package based on Synopsys?Odyssey™, the industry standard yield management system. TestChip Advantage works with TechXpress TestChip products to allow engineers to quickly extract answers from the wafer test data. It saves time by automating tedious analysis setups and by providing customized viewing of the chip experiments for random, systematic and parametric yield understanding and root cause yield loss assessment.

The TestChip Advantage templates and database captures the knowledge of the intent of the various experiments during the test chip design phase. Yield engineers are able to access wafer results (both current and historical) to analyze process issues and shifts prior to product yield loss. These capabilities allow fast wafer-level analysis, trend monitoring and identification of potential yield hits with the user-friendly menus.

Analysis Available for Various TestChip Products using TestChip Advantage
The following items will be available as part of the standard analysis:

Random and systematic defectivity for bitfail viewing (Monaco™, Indy™, Suzuka™, Silverstone™, Hockenheim™, Sepang™, Spa™ and Bonneville™ products):

Parametric analysis viewing (Time Trial™, Hi Beam™, Monza™, Brickyard™, Shanghai™, Pit Lane™, and Tomei™ products):

Process variation around the nominal design rule within a certain fail rate threshold Grouped by layer Grouped by experiment type Grouped by layer and experiment type Extraction of primary parameters for active devices Relative figures of merit allow easy prioritization among experiment groups Statistics over several lots/wafers/scribes Cp, Cpk reports Anova, N-way Anova Correlation Regression F-test T-test On Chip Variance (OCV) of selected data Trend analysis between wafers/lots Split lot capability to classify wafers based on different process equipment/recipes used Custom analysis using data mining features

product:Synopsys Testchip 2006.12 Linux
Lanaguage:english
Platform:Winxp/Win7
Size:90MB