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Synopsys Leda 2007.03 Linux

::::::English Description::::::

Synopsys’ Leda® 2007.03 is a programmable design and coding guideline checker that delivers full chip mixed-language (Verilog and VHDL) and mixed representation (RTL & gate) capabilities to speed development of complex system-on-chip (SoC) designs. Leda抯 pre-packaged rules greatly enhance a designer’s ability to check HDL code for synthesizability, simulatability, testability, reusability, and RTL/gate signoff. Leda detects clock synchronization-related bugs, isolates hard-to-time circuits, verifies layout considerations and improves DFT for higher ATPG coverage. Leda comes prepackaged with rules to improve performance of Synopsys tools, such as VCS MX, DC and Formality.


Key Benefits

  • Finds complex bugs, such as those associated with multiple clock domains using static analysis
  • Verifies consistency of design and SDC constraints for DC, PrimeTime and Astro
  • Finds design and coding guideline bottlenecks that impact simulation, synthesis, timing, DFT, ERC, and layout
  • Enables design reuse with prepackaged guidelines, such as the Reuse Methodology Manual (RMM), DesignWare® and STARC
  • Implements company specific guidelines by graphically configuring prepackaged rules
  • Create complex custom rules for syntax, semantic and hardware by reusing source code of the prepackaged rules
  • Tcl for fast prototyping and C for up to 100X performance when implementing complex hardware rules



Design Challenges
Design bugs are getting harder to isolate with the increased complexity of the designs today. Design teams are getting larger with varying level of expertise on utilizing tools for both implementing and verifying the designs, thereby, failing to maximize their investment in design flows and tools. Complex design bugs that can be detected earlier in the design flow, such as clock synchronization issues, are not getting caught until production.

Leda is a programmable design and coding guideline checker that finds both language and hardware bugs for RTL and gate designs. Leda’s capacity, performance and ability to program and check for complex hardware rules gives it the unique ability to predict and detect design bugs early in the flow. Leda’s prepackaged rules, including those for Xilinx and Altera FPGA, help designers maximize performance of tools for simulation, synthesis, formal verification, timing, DFT and layout. Leda’s powerful programming interface can be used by designers to create custom rules for detecting complex bugs, such as missing synchronizers while crossing clock domains, reconvergent logic and verifying pad directions for gate level netlists. Semiconductor companies use Leda’s programmability to create and deploy design guidelines to ensure high quality signoff at RTL and gate level.

Multi-language Support
Leda is available with support for Verilog, VHDL, SDC (available July 2004), and SystemVerilog. SystemVerilog is the unified design and verification language standard that delivers enhanced designer performance, increased verification speed, and improved verification quality

product:Synopsys Leda 2007.03 Linux