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Synopsys PrimePower 2018.06 Linux64

Synopsys PrimePower 2018.06
PrimePower has advantages over Design Power, said William Ruby, director of marketing for mixed-signal and low-power design at Synopsys. One is the tool’s ability to handle designs with potential capacities of up to 10 million instances. Another is PrimePower’s time-based analysis, which lets users view power dissipation as a function of time within a waveform display.

PrimePower models pattern-dependent, capacitive switching, short-circuit and static power consumption, considering instance-specific cell-state dependencies, glitches, multiple loads and nonlinear ramp effects.

To use PrimePower, an engineer first runs an HDL simulator and generates what Synopsys calls a PrimePower interface format (PIF) file. That contains switching activity and hierarchy information. The file is created by programming language interface routines provided with the tool. PIF files can be generated by Synopsys’ VCS Verilog, Cadence’s Verilog-XL and NC-Verilog and Model Technology’s ModelSim VHDL simulators.
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