As technology feature sizes shrink, conductors get smaller, and supply voltages reduce, the corresponding current per scaled feature size increases exponentially. These changes cause power-rail IR (voltage) drop and electromigration (EM) effects that significantly degrade performance and might cause the circuit to malfunction. To eliminate such problems, Astro-Rail™ provides an accurate and design-stage comprehensive sign-off solution for power consumption, IR drop and EM analysis for advanced-technology designs. Astro-Rail is an important component of Synopsys?Milkyway™-based Galaxy™ solution. Using Synopsys?proprietary Dynamic-Macromodeling™ technology, Astro-Rail assists in reducing time to market and ensures reliability. In Astro-Rail, IR drop and EM analysis of million gate designs are completed in minutes. Astro-Rail provides sign-off quality analysis results within five percent tolerance of HSPICE® with Star-RCXT™ parasitic extraction.
- Provides in-design physical-rail analysis for early feedback
- Delivers sign-off quality accuracy with IR drop and EM results that are within 2-3 percent tolerance of HSPICE
- Delivers highest performance and greatest capacity for system-on-chip (SoC) designs
- Saves engineering development costs with easy integration into design flows
- Accepts accurate Star-RCXT extraction results for sign-off quality
- Provides transistor-level rail analysis capability with Star-RCXT/HSPICE generated models
Astro-Rail performs full-chip gate-level power analysis in addition to IR drop and EM analyses. Power analysis accepts switching information from VCD files or through a Scheme-language interface or SAIF. After analysis is complete, color is used to highlight problematic areas in the easy-to-use graphical user interface (GUI). Interactive what-if analysis allows optimization of power-pad placement. Early rail analysis can be done before the design is complete (in-design analysis); for example, when only the power routing is done or right after the placement stage.
Astro-Rail employs proprietary Dynamic- Macromodeling technology to achieve breakthrough speed, typically 2 to 3X faster than other rail analysis tools. The hierarchical matrix solution is key for rapidly analyzing complex, hierarchical, multimillion-transistor full chip designs. Dynamic-Macromodeling with the hierarchical matrix solution reduces memory usage and improves turnaround time without sacrificing accuracy.
Astro-Rail has a strong focus on accuracy. Results from the matrix-solution engine are within 2-3 percent tolerance of HSPICE results and the resistance-extraction engine values are within 5 percent of Star-RCXT values. For power analysis, sign-off quality interconnect parasitics are provided by Star-RCXT extraction.
Analysis with Hard Macros
Astro-Rail can analyze hard macros (custom blocks in a mixed-signal design or pre-designed blocks from IP vendors) in full chip designs and show IR drop or EM violations found inside those macros. Such violations might not be detected when hard macros are analyzed outside the host system. Dynamic-Macromodeling creation uses Star-RCXT extraction.
- HP-UX 11.0
- Sun Sparc Solaris 2.7, 2.8
- Linux Redhat 7.2
product:Synopsys Astro Rail 2007.03 SP1 Linux