::::::English Description::::::
FPGA Compiler II Release Notes ——————————————————————————– These release notes present the latest information about FPGA Compiler II version T-2003.09 FC3.8 in the following sections: New Features, Enhancements, and Changes Resolved STARs For information about earlier releases of FPGA Compiler II, log on to SolvNet. To access SolvNet, Go to the SolvNet Web page at http://solvnet.synopsys.com. If prompted, enter your user name and password. (If you do not have a Synopsys user name and password, follow the instructions to register with SolvNet.) Click Release Notes in the column on the left side of the SolvNet Web page. New Features, Enhancements, and Changes FPGA Compiler II version T-2003.09 FC3.8 provides new features, enhancements, and changes as described in the following sections: Support for Altera Architectures Support for Xilinx Architectures Registered Multiplier Inference Support for Xilinx Architectures Presto Verilog Improvements Enhanced Support for Altera Architectures Enhanced Support for Xilinx Architectures Support for Altera Architectures FPGA Compiler II version T-2003.09 FC3.8 supports the following new Altera architectures: Cyclone Stratix GX Support for Xilinx Architectures FPGA Compiler II version T-2003.09 FC3.8 supports the new Xilinx Spartan-3 architecture. Registered Multiplier Inference Support for Xilinx Architectures Inference of Registered Multipliers (MULT18X18S) for Xilinx Virtex-II, Virtex-II Pro and Spartan-3 architectures is supported by FPGA Compiler II version T-2003.09 FC3.8. Presto Verilog Improvements The Presto Verilog compiler in FPGA Compiler II version T-2003.09 FC3.8 is updated to have the same behavior as Design Compiler version 2003.03-2, which has MUXOP inference issues resolved. Enhanced Support for Altera Architectures Enhanced support is added for the following Altera architectures: Stratix APEX II APEX 20KE, APEX20 KC and APEX 20K ACEX 1K FLEX10 KE MAX 7000AE and MAX 7000B Enhanced Support for Xilinx Architectures Enhanced support is added for the following Xilinx architectures: Virtex-E Virtex-II Virtex-II Pro Resolved STARs The Synopsys Technical Action Requests (STARs) listed in the following table are resolved in FPGA Compiler II version T-2003.09 FC3.8. Table 1 Resolved FPGA Compiler II STARs STAR ID 159726 160190 160730 158128 126212 144938 140964 161857 159986 159727 161891 159553 161965 160564 162053 137762 127826 108750 139659 148885 118017 165156 163980 163498 164342 160479 165861 158123 158485 FPGA Compiler II™ User Guide Contents What’s New in This Release . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xii About This Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xv Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xviii 1. About FPGA Compiler II Features and Benefits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 2. DesignWizard Synthesis Flow Understanding the DesignWizard Flow . . . . . . . . . . . . . . . . . . . . . . 2-2 Adding Design Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Selecting Target Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Specifying Optimization and Output Options . . . . . . . . . . . . . . . 2-5 Project File Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 3. Advanced Synthesis Flow Creating a Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 iv Contents Setting Project Synthesis Options . . . . . . . . . . . . . . . . . . . . . . . 3-5 Adding Design Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 Debugging Design Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 Creating an Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 Understanding the Constraints Editor . . . . . . . . . . . . . . . . . . . . . . . 3-14 Importing and Exporting Constraints . . . . . . . . . . . . . . . . . . . . . . . . 3-15 Specifying Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 Specifying Clock Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 Specifying I/O Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 Creating Subpaths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 Defining Multicycle Timing Constraints . . . . . . . . . . . . . . . . . . . . . . 3-18 Defining False Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22 Exporting a Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-23 Generating a Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25 Using Quartus II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27 4. Analyzing Design Timing Results Checking the Results of Optimization . . . . . . . . . . . . . . . . . . . . . . . 4-2 Viewing Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 Viewing a Schematic of an RTL Design. . . . . . . . . . . . . . . . . . . 4-6 Viewing a Schematic of an Optimized (Mapped) Design. . . . . . 4-7 Using the TimeTracker Timing Analysis . . . . . . . . . . . . . . . . . . . . . 4-8 v Contents 5. Using the FPGA Compiler II Shell Creating FPGA and Design Compiler Scripts . . . . . . . . . . . . . . . . . 5-2 Running Command Scripts From the Shell . . . . . . . . . . . . . . . . . . . 5-3 Understanding FST Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 FST Command Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 Project Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 FST Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 Constraint Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 Reports Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 Browsing Objects Commands . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 Timing Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 Source Design Management Commands . . . . . . . . . . . . . . . . . 5-14 Target Management Commands . . . . . . . . . . . . . . . . . . . . . . . . 5-14 Logical Library Management Commands . . . . . . . . . . . . . . . . . 5-14 Chip Management Commands . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 Source File Management Commands . . . . . . . . . . . . . . . . . . . . 5-15 Project Management Commands . . . . . . . . . . . . . . . . . . . . . . . 5-15 Built-In Tcl Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15 Other Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18 6. Using Block-Level Incremental Synthesis (BLIS) Identifying Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 Defining Block Roots Using the GUI . . . . . . . . . . . . . . . . . . . . . . . . 6-3 Defining Block Roots From the Shell. . . . . . . . . . . . . . . . . . . . . . . . 6-5 vi Contents Updating an Implementation Using BLIS . . . . . . . . . . . . . . . . . . . . 6-6 Choosing Block Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 Planning a Design for BLIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 Using BLIS With Altera Quartus II . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9 7. Using DesignWare Components Installing DesignWare Foundation. . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 Instantiating DesignWare Foundation Components . . . . . . . . . 7-4 Synthesizing DesignWare Foundation. . . . . . . . . . . . . . . . . . . . 7-5 8. Implementing Memory Elements Using Memory Elements With Altera Devices. . . . . . . . . . . . . . . . . 8-2 Using Memory Elements With Lucent Devices . . . . . . . . . . . . . . . . 8-5 Synthesizing Designs with RAM Elements . . . . . . . . . . . . . . . . 8-5 Synthesizing Designs With ROM Elements . . . . . . . . . . . . . . . . 8-8 Using Memory Devices With Xilinx Devices . . . . . . . . . . . . . . . . . . 8-10 Instantiating a LogiBLOX Element in a VHDL Design . . . . . . . . 8-10 Instantiating a LogiBLOX Element in a Verilog Design . . . . . . . 8-11 Appendix A. Using ASCII Constraint Files About the ASCII Constraint File Format . . . . . . . . . . . . . . . . . . . . . A-3 Header Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-4 Clock Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-4 Object Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-5 Path Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-6 vii Contents Port Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-7 Module Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-8 Register Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-10 Vendor Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-10 Exporting an ASCII Constraint File . . . . . . . . . . . . . . . . . . . . . . . . . A-11 Importing an ASCII Constraint File . . . . . . . . . . . . . . . . . . . . . . . . . A-12 Appendix B. Migrating From ASICs to FPGAs HDL Source Code Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3 Design Compiler Shell Script Translation . . . . . . . . . . . . . . . . . . . . B-4 Synopsys Database Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-5 Register Retiming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-5 Integration With Place and Route Tools . . . . . . . . . . . . . . . . . . . . . B-8 Appendix C. Mixing HDL and Netlist Inputs Glossary Index viii Contents ix Figures Figure 1-1 FPGA Compiler II Design Flow Overview . . . . . . . . . . . 1-2 Figure 1-2 FPGA Compiler II in Your Design Environment . . . . . . . 1-6 Figure 2-1 DesignWizard Project Dialog Box. . . . . . . . . . . . . . . . . . 2-2 Figure 2-2 Adding Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Figure 2-3 Selecting Target Devices . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Figure 2-4 Optimization Common Settings . . . . . . . . . . . . . . . . . . . 2-5 Figure 2-5 Changing Output Options . . . . . . . . . . . . . . . . . . . . . . . . 2-6 Figure 2-6 Finishing the Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 Figure 3-1 The Project Window After You Add Design Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 Figure 3-2 HDL Editor Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 Figure 3-3 Drop-Down List of Top-Level Designs in the Toolbar . . . 3-10 Figure 3-4 Create Implementation Dialog Box . . . . . . . . . . . . . . . . . 3-11 Figure 3-5 Creating the Design Implementation . . . . . . . . . . . . . . . 3-13 Figure 3-6 Constraint Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 Figure 3-7 Shift Register With Multicycle Timing Constraint Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 x Figure 3-8 New Sub Path Dialog Box . . . . . . . . . . . . . . . . . . . . . . . 3-20 Figure 3-9 Create /Edit Timing Sub Path Dialog Box . . . . . . . . . . . . 3-21 Figure 3-10 Path Constraint Table Dialog Box . . . . . . . . . . . . . . . . . . 3-22 Figure 3-11 Export Netlist Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . 3-24 Figure 3-12 Generate Project Report Dialog Box . . . . . . . . . . . . . . . 3-26 Figure 3-13 Place and Route Dialog Box. . . . . . . . . . . . . . . . . . . . . . 3-27 Figure 4-1 Optimization Results in the Clocks Constraint Table . . . 4-2 Figure 4-2 Optimization Results in the Paths Constraint Table . . . . 4-3 Figure 4-3 Optimization Results in the Ports Constraint Table. . . . . 4-3 Figure 4-4 Optimization Results in the Modules Constraint Table . . 4-4 Figure 4-5 RTL Version of a Design in the Schematic Viewer . . . . . 4-5 Figure 4-6 Optimized (Mapped) Version of a Design in the Schematic Viewer . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 Figure 6-1 Example of Blocks and Block Roots . . . . . . . . . . . . . . . . 6-3 Figure 6-2 Modules Constraint Table . . . . . . . . . . . . . . . . . . . . . . . . 6-4 Figure 6-3 Update Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 Figure 7-1 Dialog Box for Choosing FPGA Vendors and Families to Install . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 Figure B-1 Typical FPGA Compiler II Design Flow. . . . . . . . . . . . . . B-2 Figure B-2 Register Retiming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-6 Figure B-3 Pipelining Combinational Logic. . . . . . . . . . . . . . . . . . . . B-7
product:Synopsys FPGA Compiler-II 3.8
Lanaguage:english
Platform:Winxp/Win7
Size:90MB