Engineering change orders (ECOs) have a wide variety of implementations that range from adding or removing logic in a design to more subtle changes such as cleaning up routing for signal integrity. All ECOs are focused on delivering products to market as fast as possible with minimal risk to correctness and schedule. ECOs can be a time of high stress, long work hours, and uncertainty. Even if the logic change is implemented in the netlist, there might not be enough spare gates on the mask to implement the change.
Benefits
Provides faster turnaround time by minimizing manual intervention and eliminating time-consuming iterations
Generates early estimates on ECO feasibility by quantifying designer intent
Implements complex ECOs that are typically not attempted manually
Enables front-end designers in fabless semiconductor companies earlier netlist handoff to ASIC vendors
Improves designer productivity and offers flexibility to do ECO with metal-only layers, thus reducing manufacturing costs and driving faster design convergence toward tapeout
Reduces verification time significantly by using abstraction techniques to verify multi-million–gate designs much faster than traditional gate-level simulation
Decreases the risk of missing critical bugs through independent verification technology
product:cadence CONFRML 13.10
Lanaguage:english
Platform:Linux32/Linux64
Size:2DVD