Xilinx Vivado Design Suite HLx Editions 2020.2

Xilinx, Inc. announced the Vivado Design Suite HLx Editions 2020.2, enabling a new ultra high productivity approach for designing All Programmable SoCs, FPGAs, and the creation of reusable platforms.

Vivado Design Suite HLx Editions 2020.2 – Date: Nov 24, 2020

What\’s New in Vivado

Device Support

– Versal AI Core series : XCVC1902 and XCVC1802

– Versal Prime Series : XCVM1802

– Zynq UltraScale+ RFSoC: XCZU43DR, XCZU46DR, XCZU47DR, XCZU48DR, XCZU49DR

Install and Licensing

– Petalinux is now a part of the Xilinx Unified installer in addition to the existing standalone installation offering.

IP Integrator

Revision Control Improvements

– New directory structure separating sources from output products

– BD/IP output products are no longer placed in the project.srcs directory.

– All output products reside in the project.gen directory parallel to the project.srcs.

Address Map Enhancements

– Graphical view of Address Map in HTML

Vitis Platform Creation Improvements

– Ability to identify Vivado Project as an extensible platform project during Project Creation and in Project Settings​

– Add new Platform Interface validation DRCs

– Run Platform DRCs during validation for platform BDs​

– New Platform Setup GUI​

IP Caching improvements​

– Ability to create and use Read-Only zipped IP Caches ​

– Zipped Cached can be pointed to and need not be unzipped

Block Design Container

– Instantiate a BD inside another BD​

CIPS (Control, Interfaces and Processing System) – Versal

– Example Designs in XHUB stores – Versal ​

IP Enhancements

Data Center

Queue DMA Subsystem for PCI Express (QDMA) device support expansion

– Gen3x8 in "-2LV" UltraScale+ devices

– Gen4x8 in "-2LV" Virtex UltraScale+ VU23P device

Versal ACAP subsystems for PCI Express targeting GTY, PL PCIE4, and CPM4 integrated blocks

– Integrated Block for PCI Express (GTY + PL PCIE4)

– DMA and Bridge Subsystem for PCI Express (GTY + PL PCIE4 + Soft QDMA, XDMA, AXI-Bridge)

– CPM Mode for PCI Express (GTY + CPM4)

– CPM DMA and Bridge Mode for PCI Express (GTY + CPM4 + Hard QDMA, XDMA, AXI-Bridge)

– PHY for PCI Express (GTY)

Video and Imaging

MIPI

– DPHY rates on Versal devices increased: 3200Mbs on -2 and -3 devices, 3000Mbs on -1 devices

– Added YUV420 output support for CSI RX core

DisplayPort 1.4 Subsystems

– YUV420 support, Adaptive sync, Static HDR

– eDP IP option in general access

SDI subsystems

– HLG HDR support

– Versal VCK190 pass thru example design

HDMI2.0 adds support for HDCP2.3

Wired and Wireless

– JESD204C Full Production

– New 200G RS-FEC for UltraScale+ and Versal

– 1G/10G/25G Ethernet adds 1-step and TSN support

– Versal MRMAC 1-step 1588 hardware timestamping​

– 10G/25G MRMAC Ethernet 2-step 1588 linux driver support ​

Product:Xilinx Vivado Design Suite HLx Editions 2020.2
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Platform:Win7/WIN10
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