Cadence RF Methodology Kit 8.1 Linux

The Cadence® rF SiP Methodology Kit accelerates the application of eDA
technologies to system-in-package (SiP) designs for radio Frequency
(rF) and wireless applications. it provides methodologies that maximize
design productivity and predictability for customers leveraging the
advantages of SiP technology. An integrated set of products built around
proven methodologies enables complete front-to-back SiP design and
implementation. All this is demonstrated on a segment representative
design, resulting in reduced time to new products, increased functional
densities, and higher system performance.
CADENCE SIP DESIGN TECHNOLOGY
CADENCE RF SIP METHODOLOGY KIT
Manufacturers of high-performance consumer electronics are
The Cadence rF SiP Methodology Kit leverages new SiP
turning to SiP design because it can provide a number of
technologies and verified advanced methodologies for rF SiP
advantages over just SoC. in addition to reduced cost, lower
design. it enables wireless design teams to achieve predictable
power, and higher performance, SiP design offers the flexibility
design schedules by boosting design productivity while also
to mix radio rF and high-speed digital circuitry in the same
increasing the likelihood of first-pass success by improving
package. However, this also means it requires expert engineering
quality. By combining comprehensive links between system
talent in widely divergent fields. Conventional eDA solutions
design, physical implementation and manufacturing, the kit
have failed to automate the design processes required for
allows full-SiP electrical analysis and characterization of critical
efficient SiP development. By enabling and integrating design
paths as well as behavioral modeling from overall system-level
concept exploration, capture, construction, optimization, and
simulation through bottom-up verification.
validation of complex multi-chip and discrete substrate
These capabilities are demonstrated on a segment representative
assemblies on printed circuit boards (PCBs), the Cadence SiP
design (an 802.11b/g wLAN rF SiP) that includes a Helic-based
design technology streamlines the integration of multiple high-
rF transceiver and analog baseband die in a 180nm generic
pin-count chips onto a single substrate. This approach allows
CMOS process, a second AMS analog front-end baseband
companies to adopt what were once expert engineering SiP
interface die in a 90nm generic CMOS process, and embedded
design capabilities for mainstream product development.
and discrete passive off-chip components in a generic LTCC
Cadence SiP solutions seamlessly integrate into Cadence
substrate. The kit also contains re-usable, pre-configured
encounter® for die abstract codesign, Cadence virtuoso® for
components from test-benches, models, and simulation plans for
rF module design, and Cadence Allegro® for package/board
block and full SiP-level verification and physical implementation
approaches. Additionally, design teams are led through a step-
by-step example on how to apply advanced Cadence
technologies to best achieve design success.
product:Cadence RF Methodology Kit 8.1 Linux
Lanaguage:english
Platform:Winxp/Win7
Size:2.01G