Verification is the most time consuming task in ASIC design today.
Certify ASIC RTL prototyping software from the Synopsys® Synplicity®
Business Group helps accelerate the verification phase by allowing you
to build multi-FPGA based prototypes of your ASIC design in an easy,
intuitive fashion, and with no modifications to the original design. ASIC
prototypes typically deliver speeds between 10 – 80 MHz, far in excess
of any other verification technology and at a lower cost than any other
hardware solution. Previous FPGA prototyping techniques have been
difficult, cumbersome, and time consuming. The Certify solution
simplifies the prototyping process by providing an intuitive, user-friendly
tool that works directly from your RTL code combined with the
leading Quality of Results (QoR) that the Synplicity Business Group is
• Combines best-in-class technologies for a complete prototyping
• Targets Synopsys’ Synplicity Business Group HAPS prototype boards,
off-the-shelf boards, and user-created custom prototype boards.
• Advanced RTL partitioning offering fully automatic, manual, or mixed
• Automates difficult tasks such as gated-clock conversion, I/O pin
multiplexing, and signal to trace assignments.
• Features the same synthesis technology found in the best-in-class
Synplify Pro® FPGA synthesis software.
• Offers multiple debug insertion technologies.
Rapid RTL Prototyping With Multiple FPGAs
The Certify tool dramatically reduces the time required to produce a
multi-FPGA prototype. Multi-chip timing analysis and time budgeting is
built into the Certify tool, enabling simultaneous partitioning and
optimization of a design spanning multiple FPGAs. Only the Certify
product has the capacity to take a multi-million gate ASIC RTL source
and synthesize it directly into multiple FPGAs. It does this without
requiring changes to the RTL source code or having to break up the
design into many small blocks to be able to run synthesis.
product:Synopsys Certify 2011.3