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Synopsys Vera 2007.12 AMD64

the design technology leader for complex IC design, announced the immediate availability of VERA(TM) CORE, a new high-level verification tool that enables intellectual property (IP) providers and their customers to share an IP verification environment.

With VERA CORE, IP providers develop portable VERA testbenches, monitors and functional coverage reports for creating high quality IP. Their customers can easily reuse these elements to cut verification time of their system-on-a-chip(SoC) design embedding
(mathematics) embedding – One instance of some mathematical object contained with in another instance, e.g. a group which is a subgroup.
2. (theory) embedding – (domain theory) A complete partial order F in [X -> Y] is an embedding if
 the IP.

\”VERA was instrumental in our ability to bring up a robust, configurable verification environment quickly,\” said Ashish Dixit, director of VLSI VLSI: see integrated circuit.

(1) (Very Large Scale Integration) Between 100,000 and one million transistors on a chip. See SSI, MSI, LSI and ULSI.

(2) (VLSI Technology, Inc., Tempe, AZ, www.semiconductors.  Design, Tensilica, Inc. \”Automated testbench creation, constraint driven pseudo-random diagnostic generation and functional coverage capabilities provided in VERA gave us a high degree of confidence in the quality of our design. By providing an easy and secure environment to ship the VERA elements, VERA CORE helps us prove the quality of our IP to our customers. Also, by enabling reuse, VERA CORE enables our customers to bring their products to market in a shorter period of time.\”

Reusable, Portable Verification Environment

Functional verification Functional verification, in electronic design automation, is the task of verifying that the logic design conforms to specification. In everyday terms, functional verification attempts to answer the question \”Does this proposed design do what is intended?\” This is a complex task,  of IP and designs using IP have posed formidable problems to IP providers and their customers. Poor portability of the verification environment has discouraged providers from sharing their IP\’s verification environment with their customers. This has forced customers to recreate the monitors and testbenches in order to verify the integration of the IP in the embedded design. VERA CORE directly addresses both of these issues.

With VERA CORE, the IP provider generates VERA testbenches, monitors, and coverage information that can be shipped to any customer. The VERA elements are created as part of the normal verification process and VERA CORE enables free reuse of these elements by the IP customer. Normally, users of these elements would have to buy VERA license to compile them for use in a verification environment. But, when the elements are created using VERA CORE, customers can reuse them without purchasing a VERA license from Synopsys. In addition, the elements created by VERA CORE are compiled objects and hence safe for broad and secure distribution.

The IP customer uses the provided VERA elements to quickly find design problems around the IP, and in the target design. Also, the designer can use the functional coverage reports to identify missing areas in the testbench of the target design. Hence, the designer can verify the integration of the IP within their target design to create a high quality design, and get that design to market in a shorter period of time.

\”VERA CORE brings the benefits of testbench automation to the design reuse marketplace,\” said Ghulam Nurie, director of marketing for the VERA Group at Synopsys. \”With VERA CORE, IP providers can be confident that their source is protected while giving their customers an efficient, easy, ready-to-go method of verifying their system on a chip. By removing the verification bottleneck in SoC implementations, VERA CORE will accelerate functional verification of IP-based, SoC designs.\”

VERA CORE is based on the popular Synopsys VERA testbench automation tool. VERA is the only tool that can generate reactive tests, using dynamic coverage feedback to guide the stimulus generator. With VERA CORE, these tests can be reused and easily shared between the IP provider and their customer, allowing both to take advantage of the dramatic time saving benefits of VERA technology.

Broad Design for Reuse Solution for IP

VERA CORE is part of Synopsys\’ strategic framework for accelerating design reuse — launched in March of 1998 — to address the creation, integration, valuation and verification of soft and hard IP. Synopsys\’ comprehensive portfolio comprises tools and technology to address the deployment, verification and characterization of both soft and hard IP; a cost-effective distribution channel for standards-based soft IP; and partnerships and programs to aid IP providers and customers in producing and evaluating quality IP. Synopsys is the first EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board.  vendor to deliver such a broad and coordinated approach for making IP reuse a reality for the chip design community.

High Level Verification

VERA is also part of Synopsys\’ powerful, suite of functional verification products and services. In addition to testbench automation, the Synopsys solution also includes VCS (1) (Verilog Computer Simulator) See Verilog.

(2) (Version Control System) See version control. (TM), the industry\’s fastest Verilog simulator, Cyclone cyclone, atmospheric pressure distribution in which there is a low central pressure relative to the surrounding pressure. The resulting pressure gradient, combined with the Coriolis effect, causes air to circulate about the core of lowest pressure in a (R) and VSS See Vcc. (TM) for high-performance VHDL (VHSIC Hardware Description Language) A hardware description language (HDL) used to design electronic systems at the component, board and system level. VHDL allows models to be developed at a very high level of abstraction.  simulation, a comprehensive range of Logic Modeling(R) simulation models, CoverMeter(TM) code coverage analysis, and the innovative Eaglei(R) co-verification tools to help meet the challenges of functional verification of complex designs. Synopsys complements this suite with a complete static verification offering, which includes formal verification

product:Synopsys Vera 2007.12 AMD64