Designers increasingly use advanced multi-clocking architectures to meet the high-performance and low-power requirements of their chips. The 0-In® CDC verification solution focuses on the interaction between these clock domains. In fact, it addresses a number of critical verification issues that simply cannot be dealt with by simulation-based verification techniques.
An RTL or gate-level simulation of a design (that has multiple clock domains) does not accurately capture the timing related to the transfer of data between clock domains. As a consequence, simulation does not accurately predict silicon behavior, and critical bugs may escape the verification process. The 0-In CDC verification solution rectifies this problem.
The 0-In CDC verification solution sets the industry benchmark by providing the three essential elements for a complete clock-domain-crossing (CDC) verification solution: structural or static CDC analysis, CDC protocol verification, and CDC reconvergence verification. It is the only solution that enables you to accurately predict the behavior of silicon. It gives you the confidence that all of your CDC bugs will be found before tapeout and expensive respins will be avoided.
Performing clock-domain-crossing verification with 0-In CDC is straightforward. The CDC compiler analyzes the RTL code, identifies all clocks and clock domain crossings, and offers a rich, intuitive debugging environment to resolve all types of CDC issues. Once these issues are resolved, it automatically generates a set of protocol assertions and metastability models that are linked in to the simulation of the RTL code.
product:Mentor Graphics 0-In 2.6d Linux
Lanaguage:English
Platform:/Linux
Size:662MB