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Synopsys VCS 2008.12 Linux

Synopsys VCS 2008.12 Linux is the industry’s most comprehensive RTL verification solution in a single product, providing advanced bug-finding technologies, a built-in debug and visualization environment and support for all popular design and verification languages including Verilog, VHDL, SystemVerilog and SystemC™. The VCS solution’s advanced bug-finding technologies include full-featured Native Testbench, complete assertions and comprehensive code and functional coverage to find more bugs faster and easier. Additionally, the VCS Verification Library provides verification IP for today’s most popular bus standards. By natively integrating these technologies within its unique, single-compiler architecture, the VCS solution delivers up to 5X faster verification performance compared with using multiple, stand-alone tools. The VCS solution’s powerful debug and visualization environment minimizes the turnaround time to find and fix design bugs

Key Benefits

  • Full-featured, Native Testbench support for SystemVerilog and OpenVera® testbenches enables the creation of highly effective verification environments using object-oriented techniques, constrained-random stimulus and functional coverage, and provides up to 5X faster verification performance compared with stand-alone testbench tools


  • Included Synopsys VMM methodology and building-block libraries help accelerate the creation of robust, reusable verification environments following industry best practices for coverage-driven, constrained-random and assertion-based verification techniques



  • Built-in, complete support for SystemVerilog assertions (SVA) and OpenVera assertions (OVA), a library of over 50 ready-to-use checkers and the VCS Assertion IP Library for many popular interface protocol standards enable fast deployment of an assertion-based design-for-verification (DFV) methodology to speed bug detection and design quality



  • Built-in, comprehensive coverage metrics and unified coverage reporting aggregate functional, assertion, and code coverage data to provide a single view of coverage attainment against verification goals



  • Support for all popular design and verification language standards, including Verilog, VHDL, SystemVerilog and SystemC enables higher design and verification productivity and faster integration of complex SoCs built using multiple languages



  • Powerful debug and visualization environment provides easy access to design and verification data via a flexible-use model incorporating popular drag-and-drop, menu and icon-driven methods for shorter analysis and debug cycles



  • Industry-leading performance and capacity accelerate verification throughput and time-to-market



  • Integration within Synopsys\’ Discovery AMS™ solution provides the highest throughput and accuracy for mixed-signal simulations



  • Integration with other best-in-class Discovery RTL Verification Platform solutions ensures a smooth flow and complete design verification to find bugs quickly and easily.



  • Fast, native support for DesignWare® verification IP speeds verification of designs incorporating a wide range of standard interface protocols

product:Synopsys VCS 2008.12 Linux