::::::English Description::::::
The Agility Compiler provides behavioral design and synthesis for SystemC. It is a single solution for FPGA design and ASIC/SoC prototyping. Early TLM models can be quickly realized in working silicon yielding accurate design metrics and RTL for Physical design.
Better designs, faster
- Specify, design and model in SystemC
- Synthesize high-level models directly to FPGA for verification or RTL for ASIC flows using the industry’s most mature C-synthesis technology
System models in silicon earlier
- Connect the Electronic System Level with Physical design flows using the Agility Compiler
- Implement Transaction Level Models (TLM) described in SystemC in working silicon much earlier in the design flow. This capability is not restricted to small, single block or single clock domain designs.
Manage complexity and reduce risk
- Use SystemC to develop systems using layered design and transaction level modeling techniques
- Reduce error with a common language for specification through to implementation
- Maintain the testbench and share code, libraries and system models with all members of the design team from specification through to implementation.
Enable the design team
- Rapid architectural exploration in SystemC with the direct implementation of high-level models and complex algorithms
- System verification in high density reconfigurable architectures
- A common language and smooth flow to implementation
- An Easy to use design environment.
Agility Compiler in Action
For SoC developers using SystemC and Transaction Level Modeling (TLM), Agility Compiler offers a rapid path to FPGA prototypes for verification and RTL for implementation flows:
Rapid flow from SystemC algorithms and models to implementation
Rapid development from specification and architectural exploration through to synthesis and implementation.
Architectural exploration and what-if analysis of complex SystemC designs
Quickly and easily understand and explore the trade-offs between design alternatives, balancing issues such as performance, area and power.
Verify designs using the original testbench and/or RTL structural SystemC output
Reduce the verification overhead and increase designer confidence by verifying the synthesized design with the input design and original testbench
Optimized implementation
The best quality of design with a range of synthesis optimizations.
Product:Celoxica Agility Compiler v1.3 Agility
Lanaguage:english
Platform:Winxp/Win7
Size:29MB