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Mentor Graphics QuestaSim 2020.1

Mentor Graphics QuestaSim 2020.1

Mentor, a Siemens business, is pleased to announce the availability of QuestaSim 2020.1 comprehensive platform for verification complex designs. Questa is built on a core simulation and debug engine providing the industry’s most complete native support of Verilog, SystemVerilog, VHDL, SystemC, PSL and UPF.

Release Notes for QuestaSim 2020.1 – Date: Jan 28 2020

New Features Contained in this Release:

– Improved SystemVerilog performance, syntax support, extensions

– Improved VHDL performance defaults

– SystemC 2.3.2 support and default

– Visualizer Debug high performance and capacity (VIS)

– Coverage – adaptive exclusions, multibit expressions, FSM, toggle improved

– Coverage – new reporting switch from 10.7x is now default

– Legacy -novopt option is no longer supported

product:Mentor Graphics QuestaSim 2020.1
Lanaguage:english
Platform:Win7/WIN10
Size:1CD