Cadence Encounter Timing System With Encounter® Timing System, designers benefit from a consistent, integrated, multi-CPU–enabled, static timing analysis (STA) environment for place-and-route optimization and signoff verification, leading to faster design closure and better flow convergence.
To boost productivity, Encounter Timing System helps designers quickly analyze and debug multimillion-gate designs while ensuring that design intent is preserved. Global timing debug pinpoints the root cause of timing and constraint issues at the push of a button. Sophisticated delay calculation ensures accuracy and performance. Using the effective current source model (ECSM) for advanced timing, power, signal integrity (SI), and statistical delay modeling, Encounter Timing System delivers the most accurate prediction of actual silicon performance. With a competitive edge over traditional delay modeling, designers can shave weeks off of tapeout schedules.
Features/Benefits
Tightly integrated with Encounter Digital Implementation System and Encounter Power System using a common database infrastructure
Delivers a consistent STA, SI, and statistical static timing analysis (SSTA) view to optimize place-and-route, verify signoff, and achieve faster timing convergence
Eliminates the need for multiple products by integrating timing, SI, power, thermal, and SSTA analyses
Global timing debug speeds up root-cause and bottleneck analysis
Accurate and advanced analysis algorithms reduce false SI failures by 10x
Parallel processing leverages multi-CPU and distributed servers for faster throughput
Performs concurrent multi-mode/multi-corner analysis with distributed processing
Supports advanced node design through ECSMs
Delivers accurate delay calculation to within 2% of SPICE
Offers built-in critical path simulation for delay/SI correlation with SPICE
Available as a standalone solution or as part of the Encounter Digital Implementation System
product:Cadence ETS v10.1
Lanaguage:english
Platform:Linux
Size:4CD